Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

We present a mathematical de nition of a hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral speci cations of combinational and sequential devices. The HDL and the speci cation procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol. Speci cation and Veri cation of VHDL Models Technical Report #99 1